Boundary scan testing is well known, and uses a plurality of shift registers that are built into each integrated circuit. A boundary scan controller circuit is incorporated into each integrated circuit to control the transfer of data serially from one register to another. An important advantage of boundary scan testing is that it allows testing of internal logic circuitry to be conducted from external terminals. This does away with the need for probes and other instrumentation.
By way of example, a primary use of boundary scan cell designs is for circuit continuity testing. Circuit continuity testing involves loading a value into a register, and then applying a certain voltage condition to the associated pad to determine if an open or short circuit exists.
An industry standard has been implemented for boundary scan test circuits so that integrated circuits from different manufacturers may be connected in a serial chain within an electronic system. This standard is described in an industry specification, known as the IEEE JTAG 1149.1 standard. The standard provides a protocol by which various test functions may be accomplished. For example, in a JTAG scan, test circuitry and five additional JTAG test pins are added to each chip.
The standard outlines the details of the serial path of linked test registers (i.e., a boundary scan register chain) through each integrated circuit. The standard also defines the properties of a boundary scan controller circuit for each integrated circuit. The boundary scan controller circuit controls the transfer of data through the various stages of shift registers formed by the boundary scan cells within the integrated circuit.
FIG. 1 depicts a prior-art IEEE 1149.1 compliant device architecture referred to as boundary-scan architecture 310. The boundary-scan architecture 310 includes a Test Access Port (TAP) 300, a TAP Controller 200, an instruction register 260, an instruction decode logic 250, a data register bank 240, and an output stage comprising a multiplexer 270, a flip-flop 280 and a tristate buffer 290. Although the instruction decode logic 250 is shown as being separate from the instruction register 260, the instruction decode logic 250 may also be considered to be part of the instruction register 260.
A data register bank 240 includes the boundary-scan register 220 as described above, and a bypass register 210. The bypass register 210 is a single bit shift register not associated with the IC core logic (memory latches) or I/O pins. Its purpose is to provide an alternate serial path between the TDI and TDO pins of a JTAG-compliant device. As will be described below, only one of the registers in the data bank 240 forms the serial path between TDI and TDO at any given time.
The TAP 300 is the interface between the boundary-scan architecture 310 and the five IC device pins required by IEEE 1149.1. The five IC device pins are as follows: a test data in (TDI) pin and a test data out (TDO) pin, a test clock (TCK) pin, a test mode select (TMS) pin and an optional test reset (TRST) pin. During operation, a series of commands are issued through the test pins to read back data and to verify whether interconnects have been established properly.
FIG. 2 is an illustration of a typical, conventional IEEE JTAG implementation. The logic circuit includes a multiplexer 11 that selects data to be coupled to a JTAG output capture register 12 from either the core logic circuitry of the IC or from the previous scan stage. The selection is controlled by a shift/capture signal from a JTAG control logic coupled to the multiplexer 11. The capture register 12 may either be loaded externally from one of the five JTAG pins, or may comprise capture data from one of the previous test clock cycles.
The shift/capture signal enables either capture of data directly from the core logic that is normally provided to an output buffer 15, or if switched to another mode, allows the previous scan stage to be input to the capture register 12. This latter operation typically involves shifting all of the register stages of the boundary scan cell in a daisy chain fashion. The JTAG data input pin is connected to the input of the first element in the daisy chain, and the output of last element in the chain is connected to the JTAG output pin.
When the JTAG circuitry is connected in this manner, and all the registers are filled with some value, all the values may be shifted from one stage to the next until the circuitry is in a desired position. Once the shifting operation has been completed and the circuit is in a desired state, an update register 13 coupled to the capture register 12 may be used to properly align and present the data to an output buffer 15.
The output of the update register 13 is coupled to one of the inputs of a multiplexer 14. The other input of the multiplexer 14 is coupled to receive data directly from the core logic of the integrated circuit. A JTAG mode signal, which is provided from the JTAG controller, is used to select either the captured data stored in the update register 13, or the core data directly as the input to the output buffer 15. The output buffer 15 is an ordinary buffer circuit (inverter) used to drive a data signal to a pad 20. An output enable signal line 16 enables the output buffer 15.
An input buffer 25 is utilized to drive the voltage signal present at the pad 20 to either the core logic of the IC via a multiplexer 21, or to an input capture register 23 via a multiplexer 24. The multiplexer 24 selects between the output of the input buffer 25, or the previous scan stage data captured in the capture register 12. The selection is controlled by the shift/capture signal. The output of the multiplexer 24 provides the input signal to the JTAG input capture register 23. The output of the capture register 23 is provided to the update register 22, which in turn presents the captured input data back to the core logic via the multiplexer 21. As in the case with the multiplexer 14, the multiplexer 21 is controlled by the JTAG mode signal.
Signal 16 is the output of the multiplexer 34, which selects between captured data from the control update register 33. The input of the control update register 33 comes from a control capture register 32. The control capture register 32 selects between a tristate signal from the core, or data from a previous scan stage through a multiplexer 31. The multiplexer 31 is controlled by a shift/capture signal, as in the case with the multiplexers 11 and 24.
A major drawback of the existing circuitry, which is used for testing purposes, is that it is unused most of the time when a device operates in a normal mode.